1. Field of the Invention
The present invention relates generally to a semiconductor structure and a process of making the same, and more particularly, to a NAND flash circuit structure and a process of making the same.
2. Description of the Prior Art
The principle of a photolithographic process is to transfer a circuit pattern on a mask to a wafer by a method of exposure and development, thereby producing specific circuit patterns on the wafer. However, with the trend towards scaling down the semiconductor products, the conventional photolithographic technologies face formidable challenges. Takes mainstream ArF excimer laser method with wavelength of 193 nm for example, the reachable minimum half-pitch of a transistor device produced by this kind of light source during exposure in the photolithographic process is 65 nm. By incorporating the well-known immersion lithography technology, the reachable half-pitch may be further reduced to 45 nm, which is almost the physical limitation in the photolithographic processes. For this reason, if the half-pitch of the semiconductor device need to go under 45 nm, the industry needs to utilize more advanced a photo-lithographic technology, such as a double patterning technology, an extreme ultra violet (EUV) technology, a maskless photolithography (ML2) technology or a nano-imprint technology, etc.
Double patterning is one of most mature method in the aforementioned various advanced photolithography technologies. The double patterning technology enables the use of current available photolithographic tool to produce desired finer circuit patterns, without the requirement of purchasing extremely expensive advanced photolithography tools thereby avoiding huge investments. As the double patterning technology and relevant equipments gradually mature in the industry, the 193 nm immersion lithography technology once limited by the physical limits can be further applied to the advanced process nodes of 32 nm, or even 22 nm, thereby becoming the mainstream photolithographic technology for the next semiconductor generation.
The principle of the double patterning technology is to separate one fine semiconductor circuit pattern into two alternative or complementary circuit patterns. The two separate patterns will be transferred respectively by the photolithographic process and then be combined on the wafer to obtain the final completed circuit pattern. Among various double patterning technologies, negative self-aligned double patterning (N-SADP) is one of mature process already applied in the current NAND flash process flow. The N-SADP process can produce word lines or bit lines with intervals smaller than 28 nm, thereby significantly improving the memory capacity in memory blocks.
The normal N-SADP process is able to produce fine word lines with identical intervals. However, due to the process nature, the number of word lines in a single memory block produced through this process is definitely an odd number. This characteristic can not fulfill the current memory standard of an even number of word lines in one memory block.
Accordingly, it is necessary for the semiconductor industry to improve the current double patterning technology in order to overcome the aforementioned problem.